聽聽別人怎麼說
http://www.beyond3d.com/forum/viewtopic.ph...r=asc&start=800
OK. Before you even tape out the chip, you will know what types of power thresholds the chip will have ergo the theoretical target clock-speed can be calculated based on the maximum rated voltage for the process.
Now, silicon wise, as far as I can see (I’m sure there are EE’s around that will correct me) there are two main things that affect yield:
Defects: These are random issues on the silicon wafer itself, such as the silicon has not formed properly, perhaps due to a spec of dust around, or the like. On each wafer there are expected to be a number of defects and this can screw up a chip (or part of a chip).
Location: Generally speaking, so its said, the chips towards the centre of the wafer reach closer to their projected theoretical clock peaks than those towards the edge. The only vague explanation I’ve had for this so far down to the positioning of the laser when the chips are being fabricated it more optimal in the centre.
Now, of these two, defects will only affect the number of chips that each wafer will “yield” in an acceptably working fashion – the bigger the chip the more chance there is that more chips on the wafer will but fabricated on an area of the die where a defect exists; for this reason we are seeing more redundancy introduced defects are the main cause of lower performance SKU’s that have blocks disabled. The location on the wafer dictates the clockspeeds of the SKU’s – once you have cut a number of wafers you can begin to assess what clockspeeds the range of fully working chips are hitting the chips can be speed-binned for SKU categorisation via clockspeed.
Picking an arbitrary number out of the air, lets say that ATI’s calculations suggest that for the voltage their 90nm process options should be able to operate at, combined their chip projections, they could reach a theoretical target of 800MHz, which would their top end SKU may potentially reach towards (but factoring in the location issues, many/most of the chips will fall even further below this). But, another variable is yield variable is creeping in more a more frequently with smaller processes: leakage. Should a chip suffer from leakage issues this means that they may have to lower the core voltage to circumvent the issue, the net effect of lowering the core voltage the chips operate at would be to lower the clock-speed targets, not necessarily just the theoretical top end target, but potentially all those across the wafer as well.
Should leakage be the issue with R520 and the reports of chips running at 600MHz are ones that are operating at a reduced voltage, removing/reducing the leakage issue should enable them to bring the voltage back up to what the process can actually handle, hence increase the yield at higher clock rates.
(Any EE’s out there, please feel free to point out any errors in this analysis, and also point out other factors that may have a bearing on yields)
