傳說中AMD下一代處理器"打樁機Piledriver"請低調服用!

Toppc

榮譽會員
已加入
12/19/04
訊息
11,405
互動分數
230
點數
63
The CPU is just a C0 revision Bulldozer, not a Piledriver based Vishera.

CPU-Z screenshot, Ext. Model: 0<->0Fh = Orochi die (Bulldozer), 10<->1Fh = Piledriver.
The values displayed by CPU-Z are raw CPUID values, it does not matter if the software supports the chip or not.
They are always correctly detected.

Prove me wrong: CPU-Z -> Save report (TXT), post the content of lines CPUID 0x00000001 & 0x80000005.

Apologies for posting in English, my Chinese it a bit rusty.

推土機是B0 B1 B2 , 打椿機是C0
 

Basilisk

初級會員
已加入
8/8/12
訊息
4
互動分數
0
點數
0
The CPU is just a C0 revision Bulldozer, not a Piledriver based Vishera.

CPU-Z screenshot, Ext. Model: 0<->0Fh = Orochi die (Bulldozer), 10<->1Fh = Piledriver.
The values displayed by CPU-Z are raw CPUID values, it does not matter if the software supports the chip or not.
They are always correctly detected.

Prove me wrong: CPU-Z -> Save report (TXT), post the content of lines CPUID 0x00000001 & 0x80000005.

Apologies for posting in English, my Chinese it a bit rusty.

Where did you get that information? From the official Family 15h PDF? That also lists Komodo processors, but these were cancelled. Vishera is a previously not planned stop gap solution until the updated Komodo will be available sometime in 2013. Thus I assume that the PDFs are outdated in that case and therefore the rule that Piledriver has to be a Model 10h++ is not applicable.

A CPU-Z dump wont be sufficient, I would like to see an AIDA instruction latency dump.
a) Dowload AIDA here:
http://download.aida64.com/aida64extreme_build_2063_yt8p6wrjlm.zip

b)Benchmark:
right click on the status bar of the main window (bottom) -> CPU Debug -> Instruction Latency Dump

c) copy & paste results here.

Apologies for posting in English, too.

謝謝。
 
最後編輯:

The Stilt

初級會員
已加入
9/26/04
訊息
5
互動分數
0
點數
0
Where did you get that information? From the official Family 15h PDF? That also lists Komodo processors, but these were cancelled. Vishera is a previously not planned stop gap solution until the updated Komodo will be available sometime in 2013. Thus I assume that the PDFs are outdated in that case and therefore the rule that Piledriver has to be a Model 10h++ is not applicable.

A CPU-Z dump wont be sufficient, I would like to see an AIDA instruction latency dump.
a) Dowload AIDA here:
http://download.aida64.com/aida64extreme_build_2063_yt8p6wrjlm.zip

b)Benchmark:
right click on the status bar of the main window (bottom) -> CPU Debug -> Instruction Latency Dump

c) copy & paste results here.

Apologies for posting in English, too.

CPUID Extended Model: 1,2 (Family 15h) = Bulldozer µArch.
10 to 1Fh is Piledriver PERIOD.

This has nothing to do with CPU-Z or any other software.
The CPUID values are programmed at factory.

Streamroller based chips have Extended model 20-2Fh FYI.

CPUID 80000005 register will show this chip has L1DTlb4KSize of 32 (=Bulldozer) instead of the 64 (Piledriver).
 

Basilisk

初級會員
已加入
8/8/12
訊息
4
互動分數
0
點數
0
CPUID Extended Model: 1,2 (Family 15h) = Bulldozer µArch.
10 to 1Fh is Piledriver PERIOD.
Please don't shout, better answer my question first. Is your opinion based on outdated information or do you have additional information?

Streamroller based chips have Extended model 20-2Fh FYI.
Again, what is your source?
CPUID 80000005 register will show this chip has L1DTlb4KSize of 32 (=Bulldozer) instead of the 64 (Piledriver).
Ah ok, I forgot that the TLB-sizes are also encoded in the CPUIDs. I agree, that would be a sufficient proof (as long as there is not a bug ^^).

對不起,我們講英語。
 

Toppc

榮譽會員
已加入
12/19/04
訊息
11,405
互動分數
230
點數
63
這是AMD發出來並確認是打樁機初代工程樣品.目前已經入手第二版..第一版也已經繳回.
不過先講一點..這顆第二版我沒有任何資訊..剛剛開機看了一下.只知道預設時脈是3.5GHz
至於啥文件..阿災我又不是板廠RD..那會有這些東西
有新CPU我負責玩出特色就好嚕阿 ^^
 

akitetsu

進階會員
已加入
6/19/09
訊息
430
互動分數
5
點數
18
看來壓路會比較吸引我
 

FlanK3r

進階會員
已加入
2/25/10
訊息
393
互動分數
14
點數
18
年齡
43
need some comparison with the same settings with Zambezi, example in superpi32M and Cinebench.
 

The Stilt

初級會員
已加入
9/26/04
訊息
5
互動分數
0
點數
0
Please don't shout, better answer my question first. Is your opinion based on outdated information or do you have additional information?


Again, what is your source?

Ah ok, I forgot that the TLB-sizes are also encoded in the CPUIDs. I agree, that would be a sufficient proof (as long as there is not a bug ^^).

對不起,我們講英語。

Shouting was not my intention, sorry for that.

Outdated information?
Cancelled models such as Komodo and Krishna for example have nothing to do with my information being outdated :)

You forget that the Piledriver based Trinity APUs (Comal for mobile) and some of the Virgo (desktop) models have already been released.
You can check any of the CPU-Z or AIDA (if you prefer) screenshots to see what is the reported extended model.
After you are done, please check the cover page of the public #42300 BKDG document. Then download the #42301 BKDG and do the same.

There cannot be a bug in CPUID register, these are just raw generic values which can be read basically by any program. AIDA, CPU-Z, HWInfo etc will read these values correctly.

The "naming policy" of extended model identifier is ascending within the same family.
So called Bulldozer Gen.1: Interlagos, Valencia, Zambezi, Zürich = 0-0Fh (0-15 in decimal)
So called Bulldozer Gen.2 (Piledriver): Abu Dhabi, Delhi, Seoul, Trinity, Vishera = 10-1Fh (16-31 in decimal)
So called Bulldozer Gen.3 (Steamroller): Kaveri, TBA = 20-2Fh (32-47 in decimal).

Within the same µArch / die design the extended model will always be withing that range of 15 (different models possible).
 

Basilisk

初級會員
已加入
8/8/12
訊息
4
互動分數
0
點數
0
Ok apology accepted ;-)

But your arguments are precisely that what I call outdated. If I begin reading in the 42300 PDF, it starts with:
1 Overview
The AMD Family 15h Models 10h-1Fh processor (in this document referred to as the processor) is a process-
ing unit that supports x86-based instruction sets. The processor includes (a) up to two independent processing
units
referred to as compute units (each compute unit containing two cores), (b) one PCIe® root complex (in
this document referred to as the root complex or RC) with generation 2 link support, and (c) up to 2 system
memory DRAM interfaces.
There are 2 errors here, first they state that models 10h will have 4 cores max and second that there is integrated PCIe. Doesn't sound like an AM3 CPU with up to 8 cores, does it?


Then later there is section 1.5.2 called: "Major Changes Relative to Family 15h Models 00h-0Fh Processors"
CPU core changes:
• No L3 cache.

General Northbridge additions:
• Integrated graphics processor.
Another two errors: According to this information your hypothetical Vishera 10h processor has to have an integrated GPU and does not have any L3.

Obviously that characteristics are for Trinity only, and nothing else. Now you may argue that these data is not valid for Vishera, but then I ask you: Why shouldn't the model numbers be invalid, too ?

Second thing what you get wrong (but which was not the topic, yet), are the 20h models. The 42301 is not interesting for that purpose. Read the Software Optimization guide 47414 instead. There is lots of hidden information. If you read it carefully, you see Hypertransport, L3-Cache, up to 5 Modules/10 cores, quad-channel memory for 20h models etc. Nothing about PCIe, nothing about integrated graphics. Therefore this has nothing to do with the Kaveri-APU, these were the information about the canceled, Piledriver-based, Komodo, Terramar and Sepang processors, as these were announced to have up to 10cores, too. If you search for Kaveri, then watch out for Model 30h (BKDG order # 49125). There is also already a Model 40h (BKDGorder# 49127) mentioned, these are probably the next, "future CPUs", announced for 2013 based on Steamroller-cores. However, these last 2 BKDGs are obviously still under NDA and not hosted on the public AMD website.

All in all I have no reason to doubt Toppc.

regards, Basilisk
 
▌延伸閱讀