[主機板]CPU VTT Voltage Setting
- 主題發起人 piliwind
- 開始日期
根據INTEL白皮書提到關於Vtt的解釋如下:
(簡單講就是Intel驅動FSB的邏輯訊號是採用所謂的GTL+ swing的方式, Vtt是FSB中斷電壓, Vref是FSB參考電壓, 中斷電阻Rtt, 來讓FSB的訊號穩定的在low-Vss到high-Vtt中間波動, 最低跟最高電壓超出規範, 將會使FSB的訊號不穩 => 超頻不穩 )
"The signals devoted as Vtt provide termination for the front side bus and power to the I/O buffers."
"Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as VTT. Because platforms implement
separate power planes for each processor (and chipset), separate VCC and VTT supplies
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for
GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
chipsets will also provide on-die termination, thus eliminating the need to terminate the
bus on the motherboard for most GTL+ signals."
(簡單講就是Intel驅動FSB的邏輯訊號是採用所謂的GTL+ swing的方式, Vtt是FSB中斷電壓, Vref是FSB參考電壓, 中斷電阻Rtt, 來讓FSB的訊號穩定的在low-Vss到high-Vtt中間波動, 最低跟最高電壓超出規範, 將會使FSB的訊號不穩 => 超頻不穩 )
"The signals devoted as Vtt provide termination for the front side bus and power to the I/O buffers."
"Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling
technology. This technology provides improved noise margins and reduced ringing
through low voltage swings and controlled edge rates. Platforms implement a
termination voltage level for GTL+ signals defined as VTT. Because platforms implement
separate power planes for each processor (and chipset), separate VCC and VTT supplies
are necessary. This configuration allows for improved noise tolerance as processor
frequency increases. Speed enhancements to data and address busses have caused
signal integrity considerations and platform design methods to become even more
critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to
determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for
GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
chipsets will also provide on-die termination, thus eliminating the need to terminate the
bus on the motherboard for most GTL+ signals."
最後編輯：
